HCMS-2819 high performance cmos 5x7 alphanumeric ingan blue display data sheet features easy to use interfaces directly with microprocessors 0.15" character height in 8 character package rugged x- and y-stackable package serial input convenient brightness controls wave solderable low power cmos technology ttl compatible applications telecommunications equipment portable data entry devices computer peripherals medical equipment test equipment business machines avionics industrial controls description this product is a high performance, easy to use dot matrix display driven by on-board cmos ic. each display can be directly interfaced with a microprocessor, thus eliminat- ing the need for cumbersome interface components. the serial ic interface allows higher character count information displays with a minimum of data lines. the 5x7 pixel format allows the user great freedom to gener- ate user-defined characters. this product is stackable in the x- and y-directions, making it ideal for high character count displays
2 figure 1. HCMS-2819 package dimension package dimensions device selection guide description 8 digit 0.15 character height HCMS-2819 absolute maximum ratings logic supply voltage, v logic to gnd logic -0.3v to 7.0v led supply voltage, v led to gnd led -0.3v to 5.5v input voltage, any pin to gnd -0.3v to v logic +0.3v free air operating temperature range t a -40 c to +85 c relative humidity (non-condensing) 85% storage temperature, t s -55 c to 100 c maximum solder temperature solder dipping wave soldering 260 c for 5 sec 250 c for 3 sec esd protection @ 1.5 k , 100pf (each pin) class 1, 0-1999v total package power dissipation at t a =25c 2.4 w notes: for operation in high ambient temperatures , see appendix a, thermal considerations. notes: 1. dimensions are in mm (inches). 2. unless otherwise specified, tolerance on dimensions is 0.38 mm (0.015 inch). 3. lead material: solder plated copper alloy. 2.54 0.13 (0.100 0.005) (non accum.) typ. 35.56 (1.400) max. 7 6 5 4 3 2 1 0 0.25 (0.010) 7.62 (0.300) pin # 1 identifier xz coo intensity category date code (year, week) color bin country of origin part number 5.08 (0.200) 2.54 (0.100) sym. 0.51 (0.020) typ. 0.51 0.13 (0.020 0.005) 2.22 (0.087) sym. 10.16 (0.400) max. 2.11 (0.083) typ. 4.32 (0.170) typ. 1.27 (0.050) sym. 4.45 (0.175) typ. 3.71 (0.146) typ. no pin no pin v led no pin no pin no pin gnd led no pin no pin v led no pin no pin no pin data in rs no pin clock ce blank gnd logic sel v logic no pin reset osc data out pin function assignment table 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 pin # function 3 26 hcms-281x yyww
3 recommend operating conditions over temperature range (-40c to +85c) parameter symbol min. max. units logic supply voltage [1] v logic 3.0 5.5 v led supply voltage [1] v led 4.5 5.5 v gnd led to gnd logic - -0.3 +0.3 v notes: for further description, see appendix b, electrical c onsiderations, vlogic and vled considerations. electrical characteristics over operating temperature range (-40c to +85c) parameter symbol t a = 25c, v logic = 5.0v -40c< t a <85c 3.0v 4 electrical description pin function description reset (rst) sets control register bits to logic low. the dot register contents are unaffected by the reset pin. (logic low = reset; logic high = normal operation) data in (d in ) serial data input for dot or control register data. data is entered on the rising edge of the clock input. data out (d out ) serial data out put for dot or control register data. this pin is used for cascading multiple displays. clock (clk) clock input for writing dot or control register data. when chip enable is logic low, data is entered on the rising clock edge. register select (rs) selects dot register (rs = logic low) or control register (rs = logic high) as the destination for serial data entry. the logic level of rs is latched on the falling edge of the chip enable input. chip enable (ce) this input must be a logic low to write data to the display. when ce returns to logic high and clk is logic low, data is latched to either the led output drivers or a control register. oscillator select selects either an internal or external display oscillator source. (sel) (logic low = external display oscillator; logic high = internal display oscillator). oscillator (osc) output for the internal display oscillator (sel = logic high) or input for an external display oscil- lator (sel = logic low). blank (bl) blanks the display when logic high. may be modulated for brightness control. gnd led ground for led drivers gnd logic ground for logic. v led positive supply for led drivers v logic positive supply for logic.
5 ac timing characteristics over temperature range (-40 to +85c) timing diagram ref. number description symbol 4.5v 6 figure 2. write cycle timing diagram table 1. register truth table function clk ce rs select dot register not rising falling load dot register din = high, led = on din = low, led = off rising l x copy data from dot register to dot latch lhx select control register not rising falling h load control register [1,3] rising l x latch data to control word [2] lhx notes: 1. bit d 0 of control word 1 must have been preciously set to low for serial mode or high for simultaneous mode. 2. selection of control word 1 or control word 0 is set by d 7 of the control shift register. the unselected control word retains its previ- ous value. 3. control word data is loaded most significant bit (d 7 ) first. note: 1. data is copied to the control register or the dot latch and led outputs when ce is high and clk is low. t rss rsh t t clkce ces t clkh t clkl t ceh t ds t dh t cedo t dout t doutp t previous data new data 12 11 4 3 5 1 6 2 7 10 8 9 new data latched here [1] ce rs clk d in led outputs, control registers (simultaneous) out d d (serial) out dot register the dot register holds the pattern to be displayed by the leds. data is loaded into the dot register according to the procedure shown in table 1 and figure 2. first rs is brought low, then ce is brought low. next, each successive rising clk edge will shift in the data at the din pin. loading a logic high will turn the corresponding led on; a logic low turns the led off. when all 160 bits have been loaded (or 320 bits in an 8-digit display), ce is brought to logic high. when clk is next brought to logic low, new data is latched into the display dot drivers. loading data into the dot register takes place while the previous data is displayed and eliminates the need to blank the display while loading data.
7 pixel map in a 4-character display, the 160-bits are arranged as 20 columns by 8 rows. this array can be conceptualized as four 5x8 dot matrix character locations, but only 7 of the 8 rows have leds (see figure 3 & 4). the bottom row (row 0) is not used. thus, latch location 0 is never displayed. column 0 controls the left-most column. data from dot latch locations 0-7 determine whether or not pixels in column 0 are turned-on or turned off. therefore, the lower left pixel is turned-on when a logic high is stored in dot latch location 3. characters are loaded in serially, with the left-most character being loaded first and the right-most character being loaded last. by loading one character at a time and latching the data before loading the next character, the figures will appear to scroll from right to left. control register the control register allows software modification of the ics operation and consists of two independent 7-bit control words. bit d 7 in the shift register selects one of the two 7-bit control words. control word 0 performs pulse width modulation brightness control, peak pixel current brightness control, and sleep mode. control word 1 sets serial/simultaneous data out mode, and external oscillator prescaler. each function is independent of others. figure 3. pixel map figure 4. block diagram 40 bit s.r. do di data in oscillator 8 clk chip enable register select reset osc osc select blank data in clr data out control register refresh control rst prescale value h l h l l h d q rs (latched) l h current reference pwm brightness control l h l h rs (latched) ser/par mode 3:8 decoder 40 bit s.r. do di 40 bit s.r. do di 40 bit s.r. do di anode current sources v led + gnd (led) 0 char 0 column 0 column 19 char 1 char 2 char 3 row 7 dot register bit # 159 row 1 row 0 (no leds) dot registers and latches data out cathode field drivers xx xx xxxxx xxxxx xxxxx row 0 (not used) data to next character pixel data from previous character row 7 row 6 row 5 row 4 row 3 row 2 row 1
8 control register data loading data is loaded into the control register, msb first, accord- ing to the procedure shown in table 1 and figure 2. first, rs is brought to logic high and then ce is brought to logic low. next, each successive rising clk edge will shift in the data on the din pin. finally, when 8 bits have been loaded, the ce line is brought to logic high. when clk goes to logic low, new data is copied into the selected control word. loading data into the control register takes place while the previous control word configures the displays. control word 0 loading the control register with d 7 - = logic low selects control word 0 (see table 2). bits d 0 -d 3 adjust the display brightness by pulse width modulating the led on time, while bits d 4 -d 5 adjusts the display brightness by chang- table 2. control shift register ing the peak pixel current. bit d 6 selects normal operation or sleep mode. sleep mode (control word 0, bit d 6 = low) turns off the internal display oscillator and the led pixel drivers. this mode is used when the ic needs to be powered up, but does not need to be active. current draw in sleep mode is nearly zero. data in the dot register and control words are retained during sleep mode. control word 1 loading the control register with d 7 = logic high selects control word 1. this control word performs two functions: serial/simultaneous data out mode and external oscillator prescale select (see table 2). bit d 7 on-time duty relative set low pwm brightness oscillator factor brightness to select control cycles (%) (%) control word 0 l l l l 0 0 0 l l l h 1 0.2 1.7 l l h l 2 0.4 3.3 l l h h 3 0.6 5.0 l h l l 4 0.8 6.7 lhlh 5 1.0 8.3 l h h l 7 1.4 11.7 l hhh 9 1.8 15 h l l l 11 2.1 18 h l l h 14 2.7 23 hlhl 18 3.5 30 h l h h 22 4.3 37 h h l l 28 5.5 47 h h l h 36 7.0 60 hhh l 48 9.4 80 hhhh 60 11.7 100 control word 0 ld 6 d 5 d 4 d 3 d 2 d 1 d 0 peak current typical peak relative full brightness pixel current scale current control (ma) (relative brightness, %) h l 4.0 31 l h 6.4 50 l l 9.3 73 (default at power up) h h 12.8 100 sleep mode l - disables internal oscillator-display blank h - normal operation serial/simultaneous data out l - d out holds contents of bit d 7 h - d out is functionally tied to d in external display oscillator prescaler l - oscillator freq 1 h - oscillator freq 8 bit d 7 set high to select control word 1 reserved for future use (bits d 2 -d 6 must be set low) control word 1 hlllll d 1 d 0
9 serial/simultaneous data output d 0 bit d 0 of control word 1 is used to switch the mode of d out between serial and simultaneous data entry during control register writes. the default mode (logic low) is the serial d out mode. in serial mode, d out is connected to the last bit d 7 of the control shift register. storing logic high to bit d 0 changes d out to simultane- ous mode, which affects the control register only. in simultaneous mode, d out is logically connected to d in . this arrangement allows multiple ics to have their control registers written to simultaneously. for example, for n ics in the serial mode, n * 8 clock pulses to load the same data in all control registers. the propagation delay from the first ic to the last is n * t doutp . external oscillator prescaler bit d1 bit d1 of control word 1 is used to scale the frequency of an external display oscillator. when this bit is logic low, the external display oscillator directly sets the internal display clock rate. when this bit is a logic high, the external oscillator is divided by 8. this scaled frequency then sets the internal display clock rate. it takes 512 cycles of the display clock (or 8 x 512 = 4096 cycles of an external clock with the divide by 8 prescaler) to completely refresh the display once. using the prescaler bit allows the designer to use a higher external oscillator frequency without extra circuitry. this bit has no affect on the internal display oscillator frequency. bits d2-d6 these bits must always be programmed to logic low. cascaded ics figure 5 shows how two ics are connected within an hcms-281x display. the first ic controls the four left-most characters and the second ic controls the four right-most characters. the dot registers are connected in series to form a 320-bit dot shift register. the location of pixel 0 has not changed. however, dot shift register bit 0 of ic2 becomes bit 160 of the 320-bit dot shift register. the control registers of the two ics are independent of each other. this means that to adjust the display bright- ness the same control word must be entered into both ics, unless the control registers are set to simultaneous mode. longer character string systems can be built by cascad- ing multiple displays together. this is accomplished by creating a five line bus. this bus consists of ce, rs, bl, reset, and clk. the display pins are connected to the corresponding bus line. thus, all ce pins are connected to the ce bus line. similarly, bus lines for rs, bl, reset, and clk are created. then d in is connected to the right-most display. d out from this display is connected to the next display. the left-most display receives its d in from the d out of the display to its right. d out from the left-most display is not used. each display may be set to use its internal oscillator, or the displays may be synchronized by setting up one display as the master and the others as slaves. the slaves are set to receive their oscillator input from the masters oscillator output.
10 figure 5. cascaded ics. ce ic2 bits 160-319 characters 4-7 rs bl sel os c cl k d out d in ic1 bits 0-159 characters 0-3 d in rs bl sel osc clk d out ce reset reset rs bl sel osc clk d out ce reset d in appendix a. thermal considerations the display ic has a maximum junction temperature of 150c. the ic junction temperature can be calculated with equation 1 below. a typical value for r ja is 100c/w. this value is typical for a display mounted in a socket and covered with a plastic filter. the socket is soldered to a .062 in. thick pcb with .020 inch wide, one ounce copper traces. pd can be calculated as equation 2 below. figure 6 shows how to derate the power of one ic versus ambient temperature. oper ation at high ambient tem- peratures may require the power per ic to be reduced. the power consumption can be reduced by changing either the n, i pixel , osc cyc or v led . changing v logic has very little impact on the power consumption. figure 6. maximum power dissipation per ic versus ambient temperature. p max maximum power dissipation per ic - w d 0 25 t a - ambient temperature - c 0.7 0.6 0.5 0.4 0.3 0.2 0.1 60 55 50 45 40 35 30 0.8 0.9 1.0 1.1 1.2 85 80 75 70 65 90 1.3 r = 100 c/w j-a
11 appendix b. electrical considerations current calculations the peak and average display current requirements have a significant impact on power supply selection. the maximum peak current is calculated with equation 3 below. the average current required by the display can be calcu- lated with equation 4 below. the power supply has to be able to supply i peak transients and supply i led (avg) continuously. the range on v led allows noise on this supply without significantly changing the display brightness. v logic and v led considerations the display uses two independent electrical systems. one system is used to power the displays logic and the other to power the displays leds. these two systems keep the logic supply clean. separate electrical systems allow the voltage applied to v led and v logic to be varied independently. thus, v led can vary from 0 to 5.5v without affecting either the dot or the control registers. v led can be varied between 4.0 to 5.5 v without any noticeable variation in light output. however, operating v led below 4.5 v may cause objectionable mismatch between the pixels and is not recommended. dimming the display by pulse width modulating v led is also not recommended. v logic can vary from 3.0 to 5.5 v without affecting either the displayed message or the display intensity. however, operation below 4.5 v will change the timing and logic levels and operation below 3 v may cause the dot and control registers to be altered the logic ground is internally connected to the led ground by a substrate diode. this diode becomes forward biased and conducts when the logic ground is 0.4 v greater than the led ground. the led ground and the logic ground should be connected to a common ground, which can withstand the current introduced by the switching led drivers. when separate ground connections are used, the led ground can vary from -0.3 v to +0.3 v with respect to the logic ground. voltages below -0.3 v can cause all the dots to be on. voltage above +0.3 v can cause dimming and dot mismatch. using a decoupling capacitor between the power supply and ground will help prevent any supply noise in the fre- quency range greater than that of the functioning display from interfering with the displays internal circuitry. the value of the capacitor depends on the series resistance from the ground back to the power supply and the range of frequencies that need to be suppressed. it is also advan- tageous to use the largest ground plane possible. equation 1: t j max = t a + p d * r ja where: t j max = maximum ic junction temperature t a = ambient temperature surrounding the display r ja = thermal resistance from the ic junction to ambient p d = power dissipated by the ic equation 2: p d = (n * i pixel * duty factor * v led ) + i logic * v logic where: p d = total power dissipation n = number of pixels on (maximum 4 char * 5 * 7 = 140) i pixel = peak pixel current. duty factor = 1/8 * osccyc/64 osc cyc = number of on oscillator cycles per row i logic = ic logic current v logic = logic supply voltage equation 3: i peak = m * 20 * i pixel where: i peak = maximum instantaneous peak current for the display m = number of ics in the system 20 = maximum number of leds on per ic i pixel = peak current for one led equation 4: i led (avg) = n * i pixel * 1/8 * (oscillator cycles)/64 (see variable definitions above) electrostatic discharge the inputs to the ics are protected against static discharge and input current latchup. however, for best results, stan- dard cmos handling precautions should be used. before use, the hcms-281x should be stored in antistatic tubes or in conductive material. during assembly, a grounded con- ductive work area should be used and assembly personnel should wear conductive wrist straps. lab coats made of synthetic material should be avoided since they are prone to static buildup. input current latchup is caused when the cmos inputs are subjected to either a voltage below ground (v in < ground) or to a voltage higher than v logic (v in > v logic ) and when a high current is forced into the input. to prevent input current latchup and esd damage, unused inputs should be connected to either ground or v logic . voltages should not be applied to the inputs until v logic has been applied to the display.
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2010 avago technologies. all rights reserved. av02-2558en - june 29, 2010 appendix e. display brightness two ways have been shown to control the brightness of this led display: setting the peak current and setting the duty factor. both values are set in control word 0. to compute the resulting display brightness when both pwm and peak current control are used, simply multiply the two relative brightness factors. for example, if control register 0 holds the word 1001101, the peak current is 73% of full scale (bit d 5 = l, bit d 4 = l) and the pwm is set to 60% duty factor (bit d 3 = h, bit d 2 = h, bit d 1 = l, bit d 0 = h). the resulting brightness is 44% (.73 x .60 = .44) of full scale. the temperature of the display will also affect the led brightness as shown in figure 8. the temperature of the display will also affect the led brightness as shown in figure 7. appendix f. reference material application note 1027: soldering led components application note 1015: contrast enhancement tech- niques for led displays figure 7. relative luminous intensity versus ambient temperature. appendix c. oscillator the oscillator provides the internal refresh circuitry with a signal that is used to synchronize the columns and rows. this ensures that the right data is in the dot drivers for that row. this signal can be supplied from either an external source or the internal source. a display refresh rate of 100 hz or faster ensures flicker-free operation. thus for an external oscillator the frequency should be greater than or equal to 512 x 100 hz = 51.2 khz. operation above 1 mhz without the prescaler or 8 mhz with the prescaler may cause noticeable pixel to pixel mismatch. appendix d. refresh circuitry this display driver consists of 20 one-of-eight column decoders and 20 constant current sources, 1 one-of- eight row decoder and eight row sinks, a pulse width modulation control block, a peak current control block, and the circuit to refresh the leds. the refresh counters and oscillator are used to synchronize the columns and rows. the 160 bits are organized as 20 columns by 8 rows. the ic illuminates the display by sequentially turning on each of the 8 row-drivers. to refresh the display once takes 512 oscillator cycles. because there are eight row drivers, each row driver is selected for 64 (512/8) oscillator cycles. four cycles are used to briefly blank the display before the following row is switched on. thus, each row is on for 60 oscillator cycles out of a possible 64. this corresponds to the maximum led on time.
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